On Linear Skewing Schemes and d-Ordered Vectors
IEEE Transactions on Computers
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Cache and memory hierarchy design: a performance-directed approach
Cache and memory hierarchy design: a performance-directed approach
Conflict-Free Vector Access Using a Dynamic Storage Scheme
IEEE Transactions on Computers
IEEE Transactions on Computers
Architecture of an Array Processor Using a Nonlinear Skewing Scheme
IEEE Transactions on Computers
An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid
IEEE Transactions on Parallel and Distributed Systems
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Embedded DRAM technology opportunities and challenges
IEEE Spectrum
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Memory Architecture and Parallel Access
Memory Architecture and Parallel Access
Computer Architecture; A Designer's Text Based on a Generic RISC
Computer Architecture; A Designer's Text Based on a Generic RISC
IEEE MultiMedia
Two High-Bandwidth Memory Bus Structures
IEEE Design & Test
IEEE Micro
A Multiaccess Frame Buffer Architecture
IEEE Transactions on Computers
Conflict-Free Access for Streams in Multimodule Memories
IEEE Transactions on Computers
Comments on "A Multiaccess Frame Buffer Architecture"
IEEE Transactions on Computers
Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems
IEEE Transactions on Parallel and Distributed Systems
Multiskewing-A Novel Technique for Optimal Parallel Memory Access
IEEE Transactions on Parallel and Distributed Systems
Architectures for hierarchical and other block matching algorithms
IEEE Transactions on Circuits and Systems for Video Technology
A methodology to evaluate memory architecture design tradeoffs for video signal processors
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents a novel parallel memory architecture for multimedia computers. Applying a configurable or programmable addressing circuitry capable of parallel memory accesses, the memory management of multimedia applications can be enhanced. Necessary computer architecture changes to virtual address representation, paging, virtual memory, address computation circuitry and data permutation are discussed. These changes allow the memory to be partitioned for different access functions. In addition, the same memory area can be accessed by multiple access patterns. Therefore, a general-purpose computing system that is capable of exploiting the repeating memory access patterns in its applications can be built. Performance of the configurable parallel memory architecture (CPMA) is analyzed in the case of a selection of algorithms from a video encoder. These motion estimation algorithms and zigzag scanning benefit from the multiple memory access functions, which is apparent from the comparisons to the traditional sequential memory accesses.