Cost Effective VLSI Architectures for Full-SearchBlock-Matching Motion Estimation Algorithm
Journal of VLSI Signal Processing Systems - Special issue on recent development in video: algorithms, implementation and applications
BM3D: motion estimation in time dependent volume data
Proceedings of the conference on Visualization '02
A VLSI-based parallel architecture for block-matching motion estimation in video coding applications
Progress in computer research
ParNum '99 Proceedings of the 4th International ACPC Conference Including Special Tracks on Parallel Numerics and Parallel Computing in Image Processing, Video Processing, and Multimedia: Parallel Computation
Hierarchical Block Matching Motion Estimation on a Hypercube Multiprocessor
ParNum '99 Proceedings of the 4th International ACPC Conference Including Special Tracks on Parallel Numerics and Parallel Computing in Image Processing, Video Processing, and Multimedia: Parallel Computation
Configurable parallel memory architecture for multimedia computers
Journal of Systems Architecture: the EUROMICRO Journal
Efficient hierarchical motion estimation algorithm and its VLSI architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
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Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this paper, we propose two novel special-purpose architectures to implement hierarchical block matching for real-time applications. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe in details the processor architecture, the memory organization and the scheduling for both these architectures. We also show how the second architecture can be modified to handle full-search and 3-step hierarchical search block matching algorithms, with significant reduction in the hardware complexity as compared to existing architectures