A VLSI-based parallel architecture for block-matching motion estimation in video coding applications

Authors:
Donglai Xu;James M. Noras;William Booth
Affiliations:
Department of Electronic and Electrical Engineering, University of Bradford, Richmond Road, Bradford BD7 IDP, UNITED KINGDOM;Department of Electronic and Electrical Engineering, University of Bradford, Richmond Road, Bradford BD7 IDP, UNITED KINGDOM;Department of Electronic and Electrical Engineering, University of Bradford, Richmond Road, Bradford BD7 IDP, UNITED KINGDOM
Venue:
Progress in computer research
Year:
2001

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Abstract

In this paper, we proposed an efficient VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.