IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Frame-Level FSBM Motion Estimation Architecture with Large Search Range
AVSS '03 Proceedings of the IEEE Conference on Advanced Video and Signal Based Surveillance
A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast block matching algorithms for motion estimation
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 04
A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
A multilevel successive elimination algorithm for block matching motion estimation
IEEE Transactions on Image Processing
Fast block matching algorithm based on the winner-update strategy
IEEE Transactions on Image Processing
Successive elimination algorithm for motion estimation
IEEE Transactions on Image Processing
Architectures for hierarchical and other block matching algorithms
IEEE Transactions on Circuits and Systems for Video Technology
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A simple and efficient search algorithm for block-matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Fast motion vector estimation using multiresolution-spatio-temporal correlations
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
A fast rate-optimized motion estimation algorithm for low-bit-rate video coding
IEEE Transactions on Circuits and Systems for Video Technology
New fast binary pyramid motion estimation for MPEG2 and HDTV encoding
IEEE Transactions on Circuits and Systems for Video Technology
Fast full-search block matching
IEEE Transactions on Circuits and Systems for Video Technology
A novel low-power full-search block-matching motion-estimation design for H.263+
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
IEEE Transactions on Circuits and Systems for Video Technology
Global elimination algorithm and architecture design for fast block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A fast hierarchical motion vector estimation algorithm using mean pyramid
IEEE Transactions on Circuits and Systems for Video Technology
A novel modular systolic array architecture for full-search block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
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This paper addresses the development and hardware implementation of an efficient hierarchical motion estimation algorithm, HMEA, using multiresolution frames to reduce the computational complexity. Excellent estimation performance is ensured using an averaging filter to downsample the original image. At the smallest resolution, the least two motion vector candidates are selected using a full-search block matching algorithm. At the middle level, these two candidate motion vectors are employed as the center points for small range local searches. Then, at the original resolution, the final motion vector is obtained by performing a local search around the single candidate from the middle level. HMEA exhibits regular data flow and is suitable for hardware implementation. An efficient VLSI architecture that includes an averaging filter to downsample the image and two 2-D semisystolic processing element arrays to determine the sum of absolute difference in pipeline is also presented. Simulation results indicate that HMEA is more area-efficient and faster than many full-search and multiresolution architectures while maintaining high video quality. This architecture with 59K gates and 1393 bytes of RAM is implemented for a search range of [-16.0, + 15.5].