EFBLA: A Two-Phase Matching Algorithm for Fast Motion Estimation
PCM '02 Proceedings of the Third IEEE Pacific Rim Conference on Multimedia: Advances in Multimedia Information Processing
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
Efficient hierarchical motion estimation algorithm and its VLSI architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A low-power and bandwidth-efficient motion estimation IP core design using binary search
IEEE Transactions on Circuits and Systems for Video Technology
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
A content-motion-aware motion estimation for quality-stationary video coding
EURASIP Journal on Advances in Signal Processing
Adaptive search range scaling for b pictures coding
PCM'06 Proceedings of the 7th Pacific Rim conference on Advances in Multimedia Information Processing
A pipelined hardware architecture for motion estimation of H.264/AVC
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC
Journal of Signal Processing Systems
Integration, the VLSI Journal
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In this paper, a low-power full-search block matching (FSBM) motion-estimation design for the ITU-T recommendation H.263+ standard is proposed. New motion-estimation modes in H.263+ can be fully supported by our architecture. Unlike most previously presented motion-estimation chips, this design can deal with 8×8 and 16×16 block size with different searching ranges. Basically, the proposed architecture is composed of an integer pixel unit with 64 processing elements, and a half-pixel unit with interpolation, a control unit, and data registers. In order to minimize power consumption, gated-clock and dual-supply voltages are used. This design has been realized by TSMC 0.6 μm SPTM CMOS technology. The power consumption is 423.8 mW at 60 MHz and the throughput is 36 fps in CIF format