A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An efficient VLSI architecture for H.264 variable block size motion estimation
IEEE Transactions on Consumer Electronics
An efficient hardware implementation for motion estimation of AVC standard
IEEE Transactions on Consumer Electronics
A novel low-power full-search block-matching motion-estimation design for H.263+
IEEE Transactions on Circuits and Systems for Video Technology
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This paper proposes a flexible VLSI architecture design for motion estimation in H.264/AVC using a high-efficiency variable block-size decision (VBSD) approach. The proposed VBSD approach can perform a full motion search on integrating the 4 × 4 block sizes into 4 × 8, 8 × 4, 8 × 8, 8 × 16, 16 × 8, or 16 × 16 block sizes and then appropriately select the optimal modes for motion compensation operating. In other words, the proposed architecture based on the VBSD approach can effectively reduce the encoding time of the motion estimation by dealing with different block sizes under 16 × 16 searching range. Using the TSMC 0.18-μm CMOS technology, the proposed architecture has been successfully realized. Simulation and verification results show that the proposed architecture has significant bit-rate reduction and small PSNR degradation. Also, the physical chip design revealed that the maximum frame rate of this work can process 704 fps with QCIF (176 × 144), 176 fps with CIF (352 × 288) and 44 fps with 4CIF (704 × 576) video resolutions under lower gate counts and higher working frequency.