A Flexible Motion Estimation Chip for Variable Size Block Matching
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations
IEEE Transactions on Computers
Low-power H.264 video compression architectures for mobile communication
IEEE Transactions on Circuits and Systems for Video Technology
An efficient VLSI architecture for H.264 variable block size motion estimation
IEEE Transactions on Consumer Electronics
A high-performance reconfigurable VLSI architecture for vbsme in H.264
IEEE Transactions on Consumer Electronics
A novel low-power full-search block-matching motion-estimation design for H.263+
IEEE Transactions on Circuits and Systems for Video Technology
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In the Advanced Video Coding (AVC) standard, motion estimation (ME) adopts many new features to increase the coding performances such as block matching algorithm (BMA), motion vector prediction (MVP) and variable block size motion estimation (VBSME). However, VBSME is utilized in the MPEG4-AVC/H.264 standard which leads to high computational complexity and data dependency that make the hardware implementation very complex. This paper proposes a flexible VLSI architecture for full-search VBSME (FSVBSME), allowing the partitioning of the source frames into sixteen 4x4 sub-blocks and using a MVP scheme. A clock gating technique based on a distributed control unit is used for power saving. The proposed architecture was designed by Synopsys Design Compiler with 0.13@mm CMOS standard cell library. Under a clock frequency of 500MHz, it allows a power consumption of about 131mW. Our VLSI architecture, compared with contemporary ones, can offer higher processing speed, lower power consumption, lower latency and lower gate count complexity.