Maximizing memory data reuse for lower power motion estimation
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
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EURASIP Journal on Embedded Systems
Sub-block subsampling based block-matching motion estimation
AIC'04 Proceedings of the 4th WSEAS International Conference on Applied Informatics and Communications
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Complexity-Reduced ME and Interpolation Algorithms for H.264/AVC
Journal of Signal Processing Systems
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International Journal of Reconfigurable Computing
HiPC'07 Proceedings of the 14th international conference on High performance computing
Computers and Electrical Engineering
Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC
Journal of Signal Processing Systems
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This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search blockmatching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates