Image processing and data analysis: the multiscale approach
Image processing and data analysis: the multiscale approach
Kernel scheduling in reconfigurable computing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Real-Time Imaging: Theory, Techniques, and Application
Real-Time Imaging: Theory, Techniques, and Application
Digital Signal Processing for Multimedia Systems
Digital Signal Processing for Multimedia Systems
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
A block-based gradient descent search algorithm for block motion estimation in video coding
IEEE Transactions on Circuits and Systems for Video Technology
Fast motion vector estimation using multiresolution-spatio-temporal correlations
IEEE Transactions on Circuits and Systems for Video Technology
A comparison of block-matching algorithms mapped to systolic-array implementation
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Rate-distortion optimal motion estimation algorithms for motion-compensated transform video coding
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously, a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an inefficiently large number of external memory access. Recently, to reduce the number of accesses in one search block, a block matching method within a search area to reuse the search data is provided using systolic process arrays. To further reduce the data access and computation time during the block matching, we propose a new approach through the reuse of the previously-search data in two dimensions. Our new architecture in this paper is an extension from our previous work such that we reuse the previously searches area not only between two consecutive columns but also between two consecutive rows, so as to entirely remove redundant memory access. Experimental results show the efficiency of our algorithm.