VLSI Architecture for Motion Estimation using the Block-Matching Algorithm

Authors:
Cesar Sanz;Matias J. Garrido;Juan M. Meneses
Affiliations:
Dpto. de Sistemas Electrónicos y de Control. E.U.I.T. Telecomunicación;Dpto. de Sistemas Electrónicos y de Control. E.U.I.T. Telecomunicación.;Dpto. de Ingeniería Electrónica. E.T.S.I. Telecomunicación, Technical University of Madrid
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

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Abstract

In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture consists of 256 processor elements, deals with a search area of -8/+7 pels and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is implemented with ES2 0.7 micron double-metal-layer CMOS technology and works up to 20 MHz clock frequency. To simplify the hardware required for parallel connection of several devices to deal with bigger search areas, some specific features have been included. Also in this paper a comparison between this device and two commercial ICs for motion estimation is presented.