Requirements for a VLSI graphics processor
IEEE Computer Graphics and Applications
The Texas Instruments 34010 Graphics System Processor
IEEE Computer Graphics and Applications
Digital image processing (2nd ed.)
Digital image processing (2nd ed.)
Multiprocessors
Computer graphics: principles and practice (2nd ed.)
Computer graphics: principles and practice (2nd ed.)
Digital image processing (2nd ed.)
Digital image processing (2nd ed.)
Processor Arrays: Architecture and Applications
Processor Arrays: Architecture and Applications
Parallel Processing for Computer Vision and Display
Parallel Processing for Computer Vision and Display
Algorithmically Specialized Parallel Computers
Algorithmically Specialized Parallel Computers
Monolithic Architectures for Image Processing and Compression
IEEE Computer Graphics and Applications
MediaStation 5000: Integrating Video and Audio
IEEE MultiMedia
Heresy: a virtual image-space 3D rasterization architecture
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Low power motion estimation design using adaptive pixel truncation
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A Systolic Design Methodology with Application toFull-Search Block-Matching Architectures
Journal of VLSI Signal Processing Systems
Multimedia Execution Hardware Accelerator
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Real-Time MPEG-2 Video Codec System Using Multiple Digital Signal Processors
Multimedia Tools and Applications
Performance Analysis and Tuning for a Single-Chip Multiprocessor DSP
IEEE Parallel & Distributed Technology: Systems & Technology
Simulating Multimedia Systems with MVPSIM
IEEE Design & Test
Single-Chip H.324 Videoconferencing
IEEE Micro
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Real time contour tracking with a new edge detector
Real-Time Imaging
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations
IEEE Transactions on Computers
FPGA-oriented HW/SW implementation of the MPEG-4 video decoder
Microprocessors & Microsystems
Computational models for image processing for shared-memory multiprocessors
Integrated Computer-Aided Engineering
A parallel architecture for motion estimation and DCT computation in MPEG-2 encoder
ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
The sussex multimedia frame buffer
EGGH'94 Proceedings of the Ninth Eurographics conference on Graphics Hardware
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The multimedia video processor (MVP) architecture, which incorporates a variety of parallel processing techniques to deliver very high performance to a wide range of imaging and graphics applications, is described. The MVP combines, on a single semiconductor chip, multiple fully programmable processors with multiple data streams connected to shared RAMs through a crossbar network. Each of the independent processors can execute many operations in parallel every cycle. The architecture is scalable and supports different numbers of processors to meet the cost and performance requirements of different markets. MVP's target environment and the development of MVP are outlined.