Performance Analysis and Tuning for a Single-Chip Multiprocessor DSP

  • Authors:
  • Jihong Kim;Yongmin Kim

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Parallel & Distributed Technology: Systems & Technology
  • Year:
  • 1997

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Abstract

A new generation of high-performance programmable digital signal processors has a highly integrated parallel architecture, incorporating special-purpose hardware features, on-chip memory, and multiple processors into a single chip. Such single-chip multiprocessor DSPs, however, require a sophisticated performance-monitoring tool to achieve maximum performance. In this article, the authors discuss the requirements and functionality of performance-monitoring tools suitable for single-chip multiprocessor DSPs. Specifically, they describe a performance-monitoring tool that satisfies these requirements and functionality: the MVP Performance Monitor, developed for the Texas Instruments' TMS320C80 Multimedia Video Processor. They present an overview of the MPM and a general performance-tuning approach using the MPM. An 8x8 block-based 2D discrete cosine transform (DCT) implementation demonstrates the MPM's effectiveness. The authors achieved an overall speedup of 4.67 by tuning the performance based on the monitoring results from the MPM.