Performance-Measurement Tools in a Multiprocessor Environment
IEEE Transactions on Computers
Performance analysis using the MIPS R10000 performance counters
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
Performance Analysis and Tuning for a Single-Chip Multiprocessor DSP
IEEE Parallel & Distributed Technology: Systems & Technology
Pentium 4 Performance-Monitoring Features
IEEE Micro
Analyis of Path Profiling Information Generated with Performance Monitoring Hardware
INTERACT '05 Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures
Performance monitor unit design for an AXI-based multi-core SoC platform
Proceedings of the 2007 ACM symposium on Applied computing
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of high-performance system-on-chips using communication architecture tuners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the rapid development of semiconductor technology, more complicated systems have been integrated into single chips. However, system performance is not increased in proportion to the gate-count of the system. This is mainly because the optimized design of the system becomes more difficult as the systems become more complicated. Therefore, it is essential to understand the internal behavior of the system and utilize the system resources effectively in the System on Chip (SOC) design. In this paper, we design a Performance Analysis Unit (PAU) for monitoring the AMBA Advanced eXtensible Interface (AXI) bus as a mechanism to investigate the internal and dynamic behavior of an SOC, especially for internal bus activities. A case study with the PAU for an H.264 decoder application is also presented to show how the PAU is utilized in SOC platform. The PAU has the capability to measure major system performance metrics, such as bus latency, amount of bus traffic, contention between master/slave devices, and bus utilization for specific durations. This paper also presents a distributor and synchronization method to connect multiple PAUs to monitor multiple internal buses of large SOC.