Analyis of Path Profiling Information Generated with Performance Monitoring Hardware

Authors:
Alex Shye;Matthew Iyer;Tipp Moseley;David Hodgdon;Dan Fay;Vijay Janapa Reddi;Daniel A. Connors
Affiliations:
University of Colorado at Boulder;University of Colorado at Boulder;University of Colorado at Boulder;University of Colorado at Boulder;University of Colorado at Boulder;University of Colorado at Boulder;University of Colorado at Boulder
Venue:
INTERACT '05 Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures
Year:
2005

Citing 0
Cited 6

Continuous Path and Edge Profiling

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Identifying potential parallelism via loop-centric profiling

Proceedings of the 4th international conference on Computing frontiers
Shadow Profiling: Hiding Instrumentation Costs with Parallelism

Proceedings of the International Symposium on Code Generation and Optimization
A hardware hot loop path detector for dynamic parallelization and optimization

ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

Microprocessors & Microsystems
Hardware performance monitoring for the rest of us: a position and survey

NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Even with the breakthroughs in semiconductor technology that will enable billion transistor designs, hardware-based architecture paradigms alone cannot substantially improve processor performance. The challenge in realizing the full potential of these future machines is to find ways to adapt program behavior to application needs and processor resources. As such, run-time optimization will have a distinct role in future high performance systems. However, as these systems are dependent on accurate, fine-grain profile information, traditional approaches to collecting profiles at run-time result in significant slowdowns during program execution. A novel approach to low-overhead profiling is to exploit hardware Performance Monitoring Units (PMUs) present in modern microprocessors. The Itanium-2 PMU can periodically sample the last few taken branches in an executing program and this information can be used to recreate partial paths of execution. With compiler-aided analysis, the partial paths can be correlated into full paths. As statistically hot paths are most likely to occur in PMU samples, even infrequent sampling can accurately identify these paths. While traditional path profiling techniques carry a high overhead, a PMU-based path profiler represents an effective lightweight profiling alternative. This paper characterizes the PMU-based path information and demonstrates the construction of such a PMU-based path profiler for a run-time system.