A Single-Chip Multiprocessor for Multimedia: the MVP
IEEE Computer Graphics and Applications
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Reconfigurable DSP's for Efficient MPEG-4 Video and Audio Decoding
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
MPEG video decoding with the UltraSPARC visual instruction set
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
An entropy coding system for digital HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
An iterative logarithmic multiplier
Microprocessors & Microsystems
A VLSI architecture and the FPGA prototype for MPEG-2 audio/video decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an FPGA-oriented implementation methodology for the MPEG-4 video decoder based on a hardware/software co-design approach. The MPEG-4 decoder is based on MoMuSys optimized reference software combined with new hardware VLSI architectures. New architectures for input demultiplexing, variable length decoding and inverse discrete cosine transform are developed. All software and hardware structures are evaluated in terms of visual quality, computational complexity and memory bandwidth metrics. The presented implementation is compared with an optimized reference software-based solution. Simulation results demonstrate a reduction of decoder complexity, especially speed and memory bandwidth, while maintaining an acceptable quality of decoded sequences. The proposed hardware additions provide 30% speed improvement over software solution, thereby reducing the clock rate required to process full-rate video from 300MHz down to 213MHz. The MPEG-4 decoder was functionally tested on a Flextronics FPGA prototyping board.