DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Single Chip Dual–Issue RISC Processor for Real–Time MPEG–2 Software Decoding
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
VIS Speeds New Media Processing
IEEE Micro
UltraSPARC: Compiling for Maximum Floating Point Performance
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
High-Level Synthesis with SIMD Units
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Memory Performance Optimizations For Real-Time Software HDTV Decoding
Journal of VLSI Signal Processing Systems
FPGA-oriented HW/SW implementation of the MPEG-4 video decoder
Microprocessors & Microsystems
EURASIP Journal on Applied Signal Processing
| Hi-index | 0.00 |
The UltraSPARC microprocessor is equipped with a rich "visual instruction set" (VIS) which can perform ALU and other operations on several pixels in parallel. Significant performance gains are possible in the areas of video compression and decompression, as well as other areas of image processing. In this paper, we present a computational complexity analysis of MPEG video decompression, and derive a quantitative performance bound for software MPEG decoders. Based on this estimate, we show that by combining VIS and a high superscalar instruction rate, UltraSPARC is capable of decoding MPEG digital video at 720/spl times/480/spl times/30 resolution entirely in software. A coding example for the YUV to RGB colorspace conversion is also presented.