Single Chip Dual–Issue RISC Processor for Real–Time MPEG–2 Software Decoding

Authors:
Edgar Holmann;Toyohiko Yoshida;Akira Yamada;Shin-Ichi Uramoto
Affiliations:
Media Processor Architecture, System LSI Laboratory, Mitsubishi Electric Corporation, Itami, Japan;Media Processor Architecture, System LSI Laboratory, Mitsubishi Electric Corporation, Itami, Japan;Media Processor Architecture, System LSI Laboratory, Mitsubishi Electric Corporation, Itami, Japan;Media Processor Architecture, System LSI Laboratory,
Venue:
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Year:
1998

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Abstract

A single chip system for real–time MPEG–2 decoding canbe created by integrating a general purpose dual–issue RISCprocessor, with a small dedicated hardware for the variable lengthdecoding (VLD) and block loading processes; a 32KBinstruction RAM; and a 32KB data RAM. TheVLD hardware performs Huffman decoding on the input data. Theblock loader performs the half–sample prediction for motioncompensation and acts as a direct memory access (DMA) controllerfor the RISC processor by transferring data between an external2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor,running at 250MHz, is enhanced with a set of key sub-word and multimediainstructions for a sustained peak performance of 1000 MOPS. With this setupfor MPEG-2 decoding applications, bi-directionally predicted non-intra videoblocks are decoded in less than 800 cycles, leading to a single-chip,real-time MPEG-2 decoding system.