The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Next cache line and set prediction
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
167 MHz Radix-4 Floating Point Multiplier
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
MPEG video decoding with the UltraSPARC visual instruction set
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
The visual instruction set (VIS) in UltraSPARC
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
A three dimensional register file for superscalar processors
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Options for dynamic address translation in COMAs
Proceedings of the 25th annual international symposium on Computer architecture
Improving the memory-system performance of sparse-matrix vector multiplication
IBM Journal of Research and Development
The pool of subsectors cache design
ICS '99 Proceedings of the 13th international conference on Supercomputing
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
A Family of Variable-Precision Interval Arithmetic Processors
IEEE Transactions on Computers
Conflict-Free Access to Multiple Single-Ported Register Files
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
A Statistically Rigorous Approach for Improving Simulation Methodology
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Instruction-level parallel processors-dynamic and static scheduling tradeoffs
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
MaRS: a macro-pipelined reconfigurable system
Proceedings of the 1st conference on Computing frontiers
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor
IEEE Transactions on Computers
Dynamic branch prediction and control speculation
International Journal of High Performance Systems Architecture
Federation: Boosting per-thread performance of throughput-oriented manycore architectures
ACM Transactions on Architecture and Code Optimization (TACO)
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UltraSPARC-I is a general-purpose processor implementing the SPARC V9 64-bit RISC architecture. In addition to supporting this Instruction Set Architecture (ISA), UltraSPARC-I includes over 30 new multimedia instructions (VIS - Visual Instruction Set) that provide the most common operations related to image processing, two- and three-dimensional graphics, video compression/decompression algorithms, etc.The simple in-order execution model implemented on UltraSPARC-I allows a balance between a high clock rate and a relatively wide (four-issue) machine. Microarchitecture features allowing the processor to sustain an execution of four instructions per cycle even in the presence of conditional branches and cache misses are described. The second part of the article focuses on the microarchitecture features that the software can leverage to achieve higher performance, including some of the multimedia features implemented on chip.