167 MHz Radix-4 Floating Point Multiplier

Low power scalable encryption for wireless systems

Wireless Networks - Special issue VLSI in wireless networks

Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques

IEEE Transactions on Computers

On the Design of IEEE Compliant Floating Point Units

IEEE Transactions on Computers

A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication

IEEE Transactions on Computers - Special issue on computer arithmetic

Implementation of the Exponential Function in a Floating-Point Unit

Journal of VLSI Signal Processing Systems

The Flagged Prefix Adder and its Applications in Integer Arithmetic

Journal of VLSI Signal Processing Systems

UltraSparc I: A Four-Issue Processor Supporting Multimedia

IEEE Micro

To booth or not to booth

Integration, the VLSI Journal

UltraSPARC: Compiling for Maximum Floating Point Performance

COMPCON '96 Proceedings of the 41st IEEE International Computer Conference

FPU Implementations with Denormalized Numbers

IEEE Transactions on Computers

A novel IEEE rounding algorithm for high-speed floating-point multipliers

Integration, the VLSI Journal

Multi-functional floating-point MAF designs with dot product support

Microelectronics Journal

Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers

Journal of Signal Processing Systems

Variable-latency floating-point multipliers for low-power applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Bridge floating-point fused multiply-add design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications

Journal of Signal Processing Systems