Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Journal of the ACM (JACM)
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
167 MHz Radix-4 Floating Point Multiplier
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
The SNAP Project: Towards Sub-Nanosecond Arithmetic
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Reduced Latency IEEE Floating-Point Standard Adder Architectures
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
New Models of Prefix Adder Topologies
Journal of VLSI Signal Processing Systems
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
Constant addition with flagged binary adder architectures
Integration, the VLSI Journal
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speculative carry generation with prefix adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
This paper shows how a parallel prefix adder computing S = A + B may be slightly modified to yield a new adder structure, called a “flagged prefix adder”, capable of returning therelated computation pairs A + B and A + B + 1, or, if the bits of B are inverted, A − B and B − A. This adder is of use in digital communications applications and video compression, as well as arithmetic processor designs. The new adder uses 25% less transistors than the conditional-sum adder, which has been used previously in such situations.