Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Journal of the ACM (JACM)
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
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This paper introduces a variety of approaches for assessing logarithmic-depth parallel prefix adders: a delay model based on a slight modification to the Logical Effort methodology is derived; a simple area model based on wire pitch is described; a new parameter, span(i), is defined that provides a mechanism for determining cell count and whether a prefix tree exhibits idempotency. The models are tested against Knowles' Family of Adders and found to give results that are within 5% of those reported by Knowles, as well as allowing a full assessment of the family to be made. Finally, the delay and area models are used to assess the Flagged Prefix Adder, an enhanced adder capable of computing absolute differences.