A Unified Design Space for Regular Parallel Prefix Adders
Proceedings of the conference on Design, automation and test in Europe - Volume 2
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
New Models of Prefix Adder Topologies
Journal of VLSI Signal Processing Systems
Reconfigurable hardware solution to parallel prefix computation
The Journal of Supercomputing
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
ACM Transactions on Architecture and Code Optimization (TACO)
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Abstract: This paper introduces two innovations in the design of prefix adder carry trees: use of high-valency prefix cells to achieve low logical depth and end-around carry adders with reduced fan-out loading (compared with the carry select and flagged prefix adders). An algorithm for generating parallel prefix carry trees suitable for use in a VLSI synthesis tool is presented with variable parameters including carry tree width, prefix cell valency, and the spacing of repeated carry trees. The area-delay design space is mapped for a 0:25\mu mCMOS technology for a range of adder widths as a comparative study.