Boosting Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
Multilevel Reverse-Carry Addition: Single and Dual Adders
Journal of VLSI Signal Processing Systems
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
Multilevel Reverse-Carry Adder
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Unified Design Space for Regular Parallel Prefix Adders
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
New Models of Prefix Adder Topologies
Journal of VLSI Signal Processing Systems
409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Resource sharing among mutually exclusive sum-of-product blocks for area reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Design Method for Heterogeneous Adders
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
A 485ps 64-bit parallel adder in 0.18µm CMOS
Journal of Computer Science and Technology
Constant addition with flagged binary adder architectures
Integration, the VLSI Journal
Comparison of high-performance VLSI adders in the energy-delay space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
On teaching fast adder designs: revisiting ladner & fischer
Theoretical Computer Science
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area-time efficient end-around inverted carry adders
Integration, the VLSI Journal
Hi-index | 0.01 |
Binary carry-propagating addition can be efficiently expressed as a prefix computation. Several examples of adders based on such a formulation have been published, and efficient implementations are numerous. Chief among the known constructions are those of Kogge & Stone and Ladner & Fischer. In this work we show that these are end cases of a large family of addition structures, all of which share the attractive property of minimum logical depth. The intermediate structures allow trade-offs between the amount of internal wiring and the fanout of intermediate nodes, and can thus usually achieve a more attractive combination of speed and area/power cost than either of the known end-cases. Rules for the construction of such adders are given, as are examples of realistic 32b designs implemented in an industrial 0u25 CMOS process.