Depth-size trade-offs for parallel prefix computation
Journal of Algorithms
IEEE Transactions on Computers - Special issue on computer arithmetic
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
Finding optimal parallel prefix circuits with fan-out 2 in constant time
Information Processing Letters
Journal of the ACM (JACM)
Introduction to Algorithms
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
The Journal of Supercomputing
The Design and Verification of a Sorter Core
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Circuit Analysis by Non-Standard Interpretation
Proceedings of the Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits
Towards A Discipline of Dynamic Programming
Informatik bewegt: Informatik 2002 - 32. Jahrestagung der Gesellschaft für Informatik e.v. (GI)
Design Strategies for Optimal Multiplier Circuits
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Two problems in concrete complexity: cycle detection and parallel prefix computation
Two problems in concrete complexity: cycle detection and parallel prefix computation
The complexity of computations by networks
IBM Journal of Research and Development - Mathematics and computing
Teaching Hardware Description and Verification
MSE '05 Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
On the construction of zero-deficiency parallel prefix circuits with minimum depth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A functional-logic library for wired
Haskell '07 Proceedings of the ACM SIGPLAN workshop on Haskell workshop
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Much ado about two (pearl): a pearl on parallel prefix computation
Proceedings of the 35th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Operator Language: A Program Generation Framework for Fast Kernels
DSL '09 Proceedings of the IFIP TC 2 Working Conference on Domain-Specific Languages
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
Communications of the ACM
IFL'09 Proceedings of the 21st international conference on Implementation and application of functional languages
Programmable data dependencies and placements
DAMP '12 Proceedings of the 7th workshop on Declarative aspects and applications of multicore programming
Parallel programming in Haskell almost for free: an embedding of intel's array building blocks
Proceedings of the 1st ACM SIGPLAN workshop on Functional high-performance computing
A sound and complete abstraction for reasoning about parallel prefix sums
Proceedings of the 41st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages
Synchronous digital circuits as functional programs
ACM Computing Surveys (CSUR)
Hi-index | 0.00 |
A parallel prefix network of width n takes n inputs, a1, a2,. . ., an, and computes each yi = a1 ○ a2 ○ ⋅ ⋅ ⋅ ○ ai for 1 ≤ i ≤ n, for an associative operator ○. This is one of the fundamental problems in computer science, because it gives insight into how parallel computation can be used to solve an apparently sequential problem. As parallel programming becomes the dominant programming paradigm, parallel prefix or scan is proving to be a very important building block of parallel algorithms and applications. There are many different parallel prefix networks, with different properties such as number of operators, depth and allowed fanout from the operators. In this paper, ideas from functional programming are combined with search to enable a deep exploration of parallel prefix network design. Networks that improve on the best known previous results are generated. It is argued that precise modelling in a functional programming language, together with simple visualization of the networks, gives a new, more experimental, approach to parallel prefix network design, improving on the manual techniques typically employed in the literature. The programming idiom that marries search with higher order functions may well have wider application than the network generation described here.