Size-time complexity of Boolean networks for prefix computations
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
Modified-Mesh Connected Parallel Computers
IEEE Transactions on Computers
Size-time complexity of Boolean networks for prefix computations
Journal of the ACM (JACM)
Extreme Area-Time Tradeoffs in VLSI
IEEE Transactions on Computers
Optimal schedules for parallel prefix computation with bounded resources
PPOPP '91 Proceedings of the third ACM SIGPLAN symposium on Principles and practice of parallel programming
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computing Programs Containing Band Linear Recurrences on Vector Supercomputers
IEEE Transactions on Parallel and Distributed Systems
The Strict Time Lower Bound and Optimal Schedules for Parallel Prefix with Resource Constraints
IEEE Transactions on Computers
A New Class of Depth-Size Optimal Parallel Prefix Circuits
The Journal of Supercomputing
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
The Journal of Supercomputing
IEEE Transactions on Parallel and Distributed Systems
Parallel prefix computation on extended multi-mesh network
Information Processing Letters
Z4: a new depth-size optimal parallel prefix circuit with small depth
Neural, Parallel & Scientific Computations
A new approach to constructing optimal parallel prefix circuits with small depth
Journal of Parallel and Distributed Computing
The complexity of computations by networks
IBM Journal of Research and Development - Mathematics and computing
Constructing zero-deficiency parallel prefix adder of minimum depth
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
On the construction of zero-deficiency parallel prefix circuits with minimum depth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Computation-efficient parallel prefix
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel prefix algorithms on the multicomputer
WSEAS Transactions on Computer Research
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
New parallel prefix algorithms
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
New families of computation-efficient parallel prefix algorithms
WSEAS Transactions on Computers
The average time complexity to compute preffix functions in processor networks
STACS'99 Proceedings of the 16th annual conference on Theoretical aspects of computer science
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Proceedings of the 50th Annual Design Automation Conference
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