Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A Heuristic for Suffix Solutions
IEEE Transactions on Computers
Depth-size trade-offs for parallel prefix computation
Journal of Algorithms
Scans as Primitive Parallel Operations
IEEE Transactions on Computers
Limited width parallel prefix circuits
The Journal of Supercomputing
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Parallel computing using the prefix problem
Parallel computing using the prefix problem
The Strict Time Lower Bound and Optimal Schedules for Parallel Prefix with Resource Constraints
IEEE Transactions on Computers
Parallel computation: models and methods
Parallel computation: models and methods
Asynchronous Parallel Prefix Computation
IEEE Transactions on Computers
Finding optimal parallel prefix circuits with fan-out 2 in constant time
Information Processing Letters
Journal of the ACM (JACM)
A New Class of Depth-Size Optimal Parallel Prefix Circuits
The Journal of Supercomputing
Efficient parallel prefix algorithms on mulitport message-passing systems
Information Processing Letters
Scalable Hardware-Algorithms for Binary Prefix Sums
IEEE Transactions on Parallel and Distributed Systems
Prefix computations on symmetric multiprocessors
Journal of Parallel and Distributed Computing
Optimal and efficient algorithms for summing and prefix summing on parallel machines
Journal of Parallel and Distributed Computing
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
The Journal of Supercomputing
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Parallel biological sequence comparison using prefix computations
Journal of Parallel and Distributed Computing
Z4: a new depth-size optimal parallel prefix circuit with small depth
Neural, Parallel & Scientific Computations
A new approach to constructing optimal parallel prefix circuits with small depth
Journal of Parallel and Distributed Computing
Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System
The Journal of Supercomputing
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
On the construction of zero-deficiency parallel prefix circuits with minimum depth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Parallel prefix algorithms on the multicomputer
WSEAS Transactions on Computer Research
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
New parallel prefix algorithms
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
New families of computation-efficient parallel prefix algorithms
WSEAS Transactions on Computers
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
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Prefix computation is used in various areas and is considered as a primitive operation. Parallel prefix circuits are parallel prefix algorithms on the combinational circuit model. The depth of a prefix circuit is a measure of its processing time; smaller depth implies faster computation. The size of a prefix circuit is the number of operation nodes in it. Smaller size implies less power consumption, less VLSI area, and less cost. A prefix circuit with n inputs is depth-size optimal if its depth plus size equals 2n − 2. A circuit with a smaller fan-out is in general faster and occupies less VLSI area. To be of practical use, the depth and fan-out of a prefix circuit should be small. In this paper, a family of depth-size optimal, parallel prefix circuits with fan-out 2 is presented. This family of prefix circuits is easier to construct and more amenable to automatic synthesis than two other families of the same type, although the three families have the same minimum depth among all depth-size optimal prefix circuits with fan-out 2. The balanced structure of the new family is also a merit.