The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Journal of the ACM (JACM)
VLSI Implementation of Digital Fourier Transforms, Final Report
VLSI Implementation of Digital Fourier Transforms, Final Report
Two problems in concrete complexity: cycle detection and parallel prefix computation
Two problems in concrete complexity: cycle detection and parallel prefix computation
Size-time complexity of Boolean networks for prefix computations
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
Size-time complexity of Boolean networks for prefix computations
Journal of the ACM (JACM)
A Group-Theoretic Model for Symmetric Interconnection Networks
IEEE Transactions on Computers
Scans as Primitive Parallel Operations
IEEE Transactions on Computers
Extreme Area-Time Tradeoffs in VLSI
IEEE Transactions on Computers
Area-Time Optimal Adder Design
IEEE Transactions on Computers
Fast, Deterministic Routing, on Hypercubes, Using Small Buffers
IEEE Transactions on Computers
Computing Programs Containing Band Linear Recurrences on Vector Supercomputers
IEEE Transactions on Parallel and Distributed Systems
The Strict Time Lower Bound and Optimal Schedules for Parallel Prefix with Resource Constraints
IEEE Transactions on Computers
Restricted Fetch and Φ operations for parallel processing
ICS '89 Proceedings of the 3rd international conference on Supercomputing
A New Class of Depth-Size Optimal Parallel Prefix Circuits
The Journal of Supercomputing
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
The Journal of Supercomputing
Parallel prefix computation on extended multi-mesh network
Information Processing Letters
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A new synthesis technique for multilevel combinational circuits
EURO-DAC '90 Proceedings of the conference on European design automation
Z4: a new depth-size optimal parallel prefix circuit with small depth
Neural, Parallel & Scientific Computations
A new approach to constructing optimal parallel prefix circuits with small depth
Journal of Parallel and Distributed Computing
The complexity of computations by networks
IBM Journal of Research and Development - Mathematics and computing
Constructing zero-deficiency parallel prefix adder of minimum depth
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On the construction of zero-deficiency parallel prefix circuits with minimum depth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable hardware solution to parallel prefix computation
The Journal of Supercomputing
Fast and scalable computations of 2D image moments
Image and Vision Computing
Computation-efficient parallel prefix
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel prefix algorithms on the multicomputer
WSEAS Transactions on Computer Research
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
New parallel prefix algorithms
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
New families of computation-efficient parallel prefix algorithms
WSEAS Transactions on Computers
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
On-line adaptive parallel prefix computation
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
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In this paper, new upper and lower bounds are obtained for the number of gates in parallel prefix circuits with minimum depth when the number of inputs is a power of two. In addition, structural information concerning these circuits is described. Parallel prefix circuits with bounds imposed on the fan-out of the gates are also considered. In both cases, the upper and lower bounds obtained differ by small constant factors.