Restricted Fetch and Φ operations for parallel processing

Authors:
Gurindar S. Sohi;James E. Smith;James R. Goodman
Affiliations:
Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI;Department of Electrical and Computer Engineering, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI;Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI
Venue:
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Year:
1989

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Abstract

This paper discusses a restricted form of the general Fetch&&PHgr; operation and how the restricted form can be combined. In this restricted form, all processors participating in the combining have identical Fetch&&PHgr; operations. Most applications of Fetch&&PHgr; proposed in the literature satisfy the restrictions imposed. We show how this restricted form of Fetch&&PHgr; allows an easy implementation of combining, especially in bus-based multiprocessors and multiprocessors with a separate synchronization memory. Applications of the proposed restricted Fetch&&PHgr; operation are also considered.