IEEE Transactions on Computers
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
An architecture for a VLSI FFT processor
Integration, the VLSI Journal
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In the late 1970''s a modular, high-throughput architecture for large scale Fourier Transform processors was developed in [1,2]. This architecture uses only a few basic modules in a highly pipelined arrangement and some serial memory for temporary storage of operands. This streamlined architecture seemed predestined for implementation with "Charge Transfer Devices", which have proven themselves in many high-speed signal processing applications and for serial memory [3]. Thus we proposed to investigate the use of charge-coupled devices (CCDs) in the implementation of pipelined FFT processors. For various reasons which are explained below, the use of CCD''s was dropped at an early stage and the decision was made to design these same modules with standard silicon-gate NMOS technology.