An architecture for a VLSI FFT processor

Authors:
Joseph Ja'Ja';Robert Michael Owens
Affiliations:
-;-
Venue:
Integration, the VLSI Journal
Year:
1983

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Abstract

We propose a new VLSI architecture for an FFT processor. Our architecture uses few processing elements and can be laid out in a mesh-interconnected pattern. We show how to compute the discrete Fourier transform at n points with an optimal speed-up as long as the memory is large enough. The control is shown to be simple and easily implementable in VLSI.