The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Information transfer and area-time tradeoffs for VLSI multiplication
Communications of the ACM
Introduction to VLSI Systems
Area-Time Optimal VLSI Networks for Computing Integer Multiplications and Discrete Fourier Transform
Proceedings of the 8th Colloquium on Automata, Languages and Programming
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A complexity theory for VLSI
A Combinatorial Limit to the Computing Power of VLSI Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
Integration, the VLSI Journal
An architecture for a VLSI FFT processor
Integration, the VLSI Journal
Paper: Parallel strong orientation on a mesh connected computer
Parallel Computing
Hi-index | 14.98 |
This paper describes a VLSI network for the multiplication of two N-bit integers, for very large N. The network, with its area 0(N) and operation time 0(vN), matches, within a constant factor, the known theoretical O(N2) lower bound to the area × (time)2measure of complexity in the VLSI model of computation. The network, which is based on the discrete Fourier transform, has a