On the Time Required to Perform Addition
Journal of the ACM (JACM)
On the Time Required to Perform Multiplication
Journal of the ACM (JACM)
Information transfer and area-time tradeoffs for VLSI multiplication
Communications of the ACM
The Complexity of Computing
Introduction to VLSI Systems
Structure of Computers and Computations
Structure of Computers and Computations
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
The chip complexity of binary arithmetic
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Integer Division in Linear Time with Bounded Fan-In
IEEE Transactions on Computers
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
IEEE Transactions on Computers
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
The communication complexity of several problems in matrix computation
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Optimal VLSI architectures for multidimensional DFT
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
AT/sup 2/-Optimal Galois Field Multiplier for VLSI
IEEE Transactions on Computers
Upper and lower bounds on switching energy in VLSI
Journal of the ACM (JACM)
Optimal VLSI architectures for multidimensional DFT (preliminary version)
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
IEEE Transactions on Computers
AT2 bounds for a class of VLSI problems and string matching
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Comparing the combinational complexities of arithmetic functions
Journal of the ACM (JACM)
Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addition
IEEE Transactions on Computers
An Optimal Multiplication Algorithm on Reconfigurable Mesh
IEEE Transactions on Parallel and Distributed Systems
A systolic multiplier unit and its VLSI design
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A VLSI layout for a pipelined Dadda multiplier
ACM Transactions on Computer Systems (TOCS)
A Period-Processor-Time-Minimal Schedule for Cubical Mesh Algorithms
IEEE Transactions on Parallel and Distributed Systems
Optimal VLSI Networks for Multidimensional Transforms
IEEE Transactions on Parallel and Distributed Systems
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Measuring energy consumption in VLSI circuits: A foundation
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
The chip complexity of binary arithmetic
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
Multi-dimensional systolic networks, for discrete fourier transform
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Evolutionary Synthesis of Arithmetic Circuit Structures
Artificial Intelligence Review
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Evolutionary synthesis of arithmetic circuit structures
Artificial intelligence in logic design
A Mesh-Connected Area-Time Optimal VLSI Multiplier of Large Integers
IEEE Transactions on Computers
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
IEEE Transactions on Computers
Area Time Optimal VLSI Circuits for Convolution
IEEE Transactions on Computers
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
Power scalability in a mesh-connected reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS)
VLSI systolic arrays for band matrix multiplication
Integration, the VLSI Journal
Really fast syndrome-based hashing
AFRICACRYPT'11 Proceedings of the 4th international conference on Progress in cryptology in Africa
Smaller decoding exponents: ball-collision decoding
CRYPTO'11 Proceedings of the 31st annual conference on Advances in cryptology
The potential of on-chip multiprocessing for QCD machines
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
New area-time lower bounds for the multidimensional DFT
CATS 2011 Proceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 119
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