Area-time optimal VLSI integer multiplier with minimum computation time
Information and Control
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Faster Modular Multiplication by Operand Scaling
CRYPTO '91 Proceedings of the 11th Annual International Cryptology Conference on Advances in Cryptology
Performance-Scalable Array Architectures for Modular Multiplication
Journal of VLSI Signal Processing Systems
Exponentiation Using Division Chains
IEEE Transactions on Computers
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Architecture for Montgomery Multiplication
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
High-Radix Design of a Scalable Modular Multiplier
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Dual-residue montgomery multiplication
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Bipartite modular multiplication
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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The value of using a higher radix for modular multiplication in the context of RSA is investigated. The main conclusion is that for algorithms which perform the multiplication via repeated addition, there is, broadly speaking, a direct trade-off between space and time provided by change of radix. Thus chip area utilized is roughly proportional to speed. However, initially, as the radix is increased from 2, there is a short-lived increase in speed greater than the extra area used.