A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Simple Radix-4 Division with Operands Scaling
IEEE Transactions on Computers
Higher-Radix Division Using Estimates of the Divisor and Partial Remainders
IEEE Transactions on Computers
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addition
IEEE Transactions on Computers
Architectural tradeoff in implementing RSA processors
ACM SIGARCH Computer Architecture News
Comparison of Three Modular Reduction Functions
CRYPTO '93 Proceedings of the 13th Annual International Cryptology Conference on Advances in Cryptology
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Simulations of modular multipliers on FPGA
AsiaMS '07 Proceedings of the IASTED Asian Conference on Modelling and Simulation
High-speed implementation methods for RSA scheme
EUROCRYPT'92 Proceedings of the 11th annual international conference on Theory and application of cryptographic techniques
RSA moduli with a predetermined portion: techniques and applications
ISPEC'08 Proceedings of the 4th international conference on Information security practice and experience
Finite field arithmetic for cryptography
IEEE Circuits and Systems Magazine
Revisiting sum of residues modular multiplication
Journal of Electrical and Computer Engineering
Robust finite field arithmetic for fault-tolerant public-key cryptography
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Fast truncated multiplication for cryptographic applications
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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There are a number of techniques known for speeding up modular multiplication, which is the main arithmetic operation in RSA cryptography. This note shows how to gain speed by scaling the modulus. Resulting hardware is limited only by the speed of addition. Detailed analysis of fan out shows that over existing methods the speedup is potentially as much as two-fold. This is because the addition and fan out can now be done in parallel. Of course, in RSA the modulus can be chosen to need no scaling, so that most of the minor extra costs are eliminated.