Simulations of modular multipliers on FPGA

Authors:
Yinan Kong;Braden Phillips
Affiliations:
The University of Adelaide;The University of Adelaide
Venue:
AsiaMS '07 Proceedings of the IASTED Asian Conference on Modelling and Simulation
Year:
2007

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Abstract

A diverse variety of algorithms and architectures for modular multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.