High-speed implementation methods for RSA scheme

Authors:
Keiichi Iwamura;Tsutomu Matsumoto;Hideki Imai
Affiliations:
Canon Research Center, Kanagawa, Japan;Yokohama National University, Division of Electrical & Computer Engineering, Yokohama, Japan;Yokohama National University, Division of Electrical & Computer Engineering, Yokohama, Japan
Venue:
EUROCRYPT'92 Proceedings of the 11th annual international conference on Theory and application of cryptographic techniques
Year:
1992

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Abstract

This paper proposes two novel implementation methods for the RSA cryptographic scheme. (1) The most efficient RSA implementation known to the present authors. This implementation achieves 50 Kbps at about 25 Kgates for a 512-bit exponent e and a 512-bit modulus N. Thus the efficiency is 2.0 bps/gate. (2) A systolic architecture useful for high-speed and efficient and flexible chip implementation of the RSA scheme.