VLSI implementation of public-key encryption algorithms
Proceedings on Advances in cryptology---CRYPTO '86
Proceedings on Advances in cryptology---CRYPTO '86
Fast RSA-hardware: dream or reality
Lecture Notes in Computer Science on Advances in Cryptology-EUROCRYPT'88
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A Survey of Hardware Implementation of RSA (Abstract)
CRYPTO '89 Proceedings of the 9th Annual International Cryptology Conference on Advances in Cryptology
A Computer Algorithm for Calculating the Product AB Modulo M
IEEE Transactions on Computers
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
IEEE Transactions on Computers
How to securely replicate services
ACM Transactions on Programming Languages and Systems (TOPLAS)
RSA Acceleration with Field Programmable Gate Arrays
ACISP '99 Proceedings of the 4th Australasian Conference on Information Security and Privacy
Modular Exponentiation on Fine-Grained FPGA
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Systolic Modular Multiplication
CRYPTO '90 Proceedings of the 10th Annual International Cryptology Conference on Advances in Cryptology
A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Hardware architectures for public key cryptography
Integration, the VLSI Journal
High-speed implementation methods for RSA scheme
EUROCRYPT'92 Proceedings of the 11th annual international conference on Theory and application of cryptographic techniques
| Hi-index | 0.00 |
The latest improvements of RSA chips are based on progress in implementation technology and strategy i.e. smaller circuits and higher clock frequencies. There has been no improvements in efficiency of the algorithms. The efficiency is here defined as the number of bits produced pr. 1000 clock cycles.We present algorithms which improve the efficiency by 300%-400%. The main strategy is multiple bit scan and parallel execution of two multiplications. Using these algorithms and the presented hardware architecture a bit rate greater than 90 Kbit/sec. can be achieved encrypting 512 bit blocks.