RSA Acceleration with Field Programmable Gate Arrays

  • Authors:
  • Alexander Tiountchik;Elena Trichina

  • Affiliations:
  • -;-

  • Venue:
  • ACISP '99 Proceedings of the 4th Australasian Conference on Information Security and Privacy
  • Year:
  • 1999

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Abstract

An efficient implementations of modular exponentiation, i.e., the main building block in the RSA cryptographic scheme, is achieved by first designing a bit-level systolic array such that the whole procedure of modular exponentiation can be carried out entirely by a single unit without using global interconnections or memory to store intermediate results, and then mapping this design onto Xilinx XC6000 Field Programmable Gate Array.