Scalable Algorithm for Montgomery Multiplication and Its Implementation on the Coarse-Grain Reconfigurable Chip

  • Authors:
  • Elena Trichina;Alexander Tiountchik

  • Affiliations:
  • -;-

  • Venue:
  • CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
  • Year:
  • 2001

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Abstract

One approach to achieve real-time cryptography is to use reconfigurable hardware, where different cryptographical methods can be implemented with performance of special-purpose chips, but with a fraction of the time to market expense. While there is a lot of development done for fine-grain reconfigurable hardware, such as FPGAs, the area of coarse-grain programmable hardware is almost unknown. In this paper we describe a coarse-grain reconfigurable chip XPU128. This chip is capable of performing simultaneously up to 128 multiply-accumulate operations on 32-bit numbers in one clock cycle. As a case study we implemented Montgomery Multiplication. Our implementation is fully scalable, with the time increasing linearly with the length of the operands.