VLSI array processors
Computer arithmetic algorithms
Computer arithmetic algorithms
A survey of hardware implementations of RSA (abstract)
CRYPTO '89 Proceedings on Advances in cryptology
Bit-level systolic arrays for modular multiplication
Journal of VLSI Signal Processing Systems - Special issue: algorithms and parallel VSLI architecture
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation
IEEE Transactions on Computers - Special issue on computer arithmetic
IEEE Transactions on Computers
Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addition
IEEE Transactions on Computers
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Systolic Modular Multiplication
IEEE Transactions on Computers
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
IEEE Transactions on Computers
An HMAC processor with integrated SHA-1 and MD5 algorithms
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A high-performance platform-based SoC for information security
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design of a scalable RSA and ECC crypto-processor
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low-power techniques for network security processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-level design space exploration for security processor prototyping in analytical approaches
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An 830mW, 586kbps 1024-bit RSA chip design
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
The Journal of Supercomputing
A new modular exponentiation architecture for efficient design of RSA cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new algorithm for high-speed modular multiplication design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Power-Aware scheduling for parallel security processors with analytical models
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
High-Speed RSA crypto-processor with radix-4 modular multiplication and chinese remainder theorem
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
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We propose a radix-4 modular multiplication algorithm based on Montgomery's algorithm, and a fast radix-4 modular exponentiation algorithm for Rivest, Shamir, and Adleman (RSA) public-key cryptosystem. By modifying Booth's algorithm, a radix-4 cellular-array modular multiplier has been designed and simulated. The radix-4 modular multiplier can be used to implement the RSA cryptosystem. Due to reduced number of iterations and pipelining, our modular multiplier is four times faster than a direct radix-2 implementation of Montgomery's algorithm, the time to calculate a modular exponentiation is about n2 clock cycles, where n is the word length, and the clock cycle is roughly the delay time of a full adder. The utilization of the array multiplier is 100% when we interleave consecutive exponentiations. Locality, regularity, and modularity make the proposed architecture suitable for very large scale integration implementation. High-radix modular-array multipliers are also discussed, at both the bit level and digit level. Our analysis shows that, in terms of area-time product, the radix-4 modular multiplier is the best choice.