Requirements-based design evaluation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Software accelerated functional fault simulation for data-path architectures
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Unifying carry-sum and signed-digital number representations for low power
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
High-level synthesis techniques for reducing the activity of functional units
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
On testable multipliers for fixed-width data path architectures
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Radix 2 Division with Over-Redundant Quotient Selection
IEEE Transactions on Computers
A Fast Binary Adder with Conditional Carry Generation
IEEE Transactions on Computers
Power comparisons for barrel shifters
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
IEEE Transactions on Computers
Division-and-Accumulation over GF(2m)
IEEE Transactions on Computers
Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation
IEEE Transactions on Computers
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Parallel Compensation of Scale Factor for the CORDIC Algorithm
Journal of VLSI Signal Processing Systems
Design of a High-Speed Square Generator
IEEE Transactions on Computers
Comments on Duprat and Muller's Branching CORDIC Paper
IEEE Transactions on Computers
IEEE Transactions on Computers
A CAD framework for generating self-checking multipliers based on residue codes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture
Journal of VLSI Signal Processing Systems
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
On the Design of IEEE Compliant Floating Point Units
IEEE Transactions on Computers
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Number-Theoretic Test Generation for Directed Rounding
IEEE Transactions on Computers - Special issue on computer arithmetic
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
IEEE Transactions on Computers - Special issue on computer arithmetic
Optimal Left-to-Right Binary Signed-Digit Recoding
IEEE Transactions on Computers - Special issue on computer arithmetic
A Floating Point Vectoring Algorithm Based on Fast Rotations
Journal of VLSI Signal Processing Systems - special issue on CORDIC
Boosting Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Imprecise data computation for high performance asynchronous processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Testing Schemes for FIR Filter Structures
IEEE Transactions on Computers
Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
Journal of VLSI Signal Processing Systems
Environment Modelling for Robot Navigation Using VLSI-Efficient Logarithmic Approximation Method
Journal of Intelligent and Robotic Systems
A Dedicated Circuit for Charged Particles Simulation Using the MonteCarlo Method
Journal of VLSI Signal Processing Systems
The Symmetric Table Addition Method for Accurate Function Approximation
Journal of VLSI Signal Processing Systems
Towards a general framework for FPGA based image processing using hardware skeletons
Parallel Computing - Parallel computing in image and video processing
Konrad Zuse's Legacy: The Architecture of the Z1 and Z3
IEEE Annals of the History of Computing
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Fault-Secure Parity Prediction Booth Multipliers
IEEE Design & Test
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
IEEE Transactions on Computers
Long and Fast Up/Down Counters
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
Integration, the VLSI Journal
Integer and Floating Point Matrix-Vector Multiplication on the Reconfigurable Mesh
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Timing for Associative Operations on the MASC Model
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Logarithmic Number System for Low-Power Arithmetic
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A JPEG Chip for Image Compression and Decompression
Journal of VLSI Signal Processing Systems
Future Generation Computer Systems - Special issue: Geometric numerical algorithms
A dedicated circuit for charged particles simulation using the Monte Carlo method
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Accurate Function Approximations by Symmetric Table Lookup and Addition
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A Fast Optimal Robust Path Delay Fault Testable Adder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Evolvable Platform for Array Processing: A One-Chip Approach
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
(Quasi-) Linear Path Delay Fault Tests for Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Parameterizable Testing Scheme for FIR Filters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Deterministic BIST for RNS Adders
IEEE Transactions on Computers
New power-of-2 RNS scaling scheme for cell-based IC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Evolutionary Synthesis of Arithmetic Circuit Structures
Artificial Intelligence Review
A Cost-Effective Pipelined Divider with a Small Lookup Table
IEEE Transactions on Computers
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
Encyclopedia of Computer Science
Encyclopedia of Computer Science
Exploring the design space of LUT-based transparent accelerators
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication
Journal of VLSI Signal Processing Systems
Evolutionary synthesis of arithmetic circuit structures
Artificial intelligence in logic design
A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Truncated Online Arithmetic with Applications to Communication Systems
IEEE Transactions on Computers
Efficient FPGA hardware development: A multi-language approach
Journal of Systems Architecture: the EUROMICRO Journal
A developing approach of the space-based SIFP using rectangular algorithm
Signal Processing - Special section: Multimodal human-computer interfaces
A hardware-efficient programmable FIR processor using input-data and tap folding
EURASIP Journal on Applied Signal Processing
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach
IEEE Transactions on Computers
IP-checksum incremental update method proposal for efficient use of energy in wireless environments
EATIS '07 Proceedings of the 2007 Euro American conference on Telematics and information systems
A pipelined divider with a small lookup table
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
Boolean circuit programming: A new paradigm to design parallel algorithms
Journal of Discrete Algorithms
Finding Efficient Circuits Using SAT-Solvers
SAT '09 Proceedings of the 12th International Conference on Theory and Applications of Satisfiability Testing
Redundant binary partial product generators for compact accumulation in Booth multipliers
Microelectronics Journal
A new speculative addition architecture suitable for two's complement operations
Proceedings of the Conference on Design, Automation and Test in Europe
A new compact SD2 positive integer triangular array division circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
The Krawczyk algorithm: rigorous bounds for linear equation solution on an FPGA
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Sign change fault attacks on elliptic curve cryptosystems
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
On solving the partial MAX-SAT problem
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
On teaching fast adder designs: revisiting ladner & fischer
Theoretical Computer Science
An efficient parity detection technique using the two-moduli set {2h-1,2h+1}
Information Sciences: an International Journal
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