Computer arithmetic algorithms
Computer arithmetic algorithms
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesis of multiplier-less FIR filters with minimum number of additions
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Fundamentals of Computer Alori
Fundamentals of Computer Alori
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple processor core design for DCT/IDCT
IEEE Transactions on Circuits and Systems for Video Technology
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Layout-driven architecture synthesis for high-speed digital filters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 43rd annual Design Automation Conference
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Optimization of area in digital FIR filters using gate-level metrics
Proceedings of the 44th annual Design Automation Conference
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Design of low complexity digital FIR filters
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Area-reducing sharing of mutually exclusive multiplier, MAC, adder and subtractor blocks
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Search algorithms for the multiple constant multiplications problem: Exact and approximate
Microprocessors & Microsystems
Domain-Specific Optimization of Signal Recognition Targeting FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Design of low-power multiple constant multiplications using low-complexity minimum depth operations
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Optimization Algorithms for the Multiplierless Realization of Linear Transforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding the optimal tradeoff between area and delay in multiple constant multiplications
Microprocessors & Microsystems
Efficient arithmetic sum-of-product (SOP) based multiple constant multiplication (MCM) for FFT
Proceedings of the International Conference on Computer-Aided Design
Integration, the VLSI Journal
Multiple tunable constant multiplications: algorithms and applications
Proceedings of the International Conference on Computer-Aided Design
Design of digit-serial FIR filters: algorithms, architectures, and a CAD tool
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of low-complexity digital finite impulse response filters on FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the constant coefficient multiplications required in filters. The complexity of multiplier blocks can be significantly reduced by using an efficient number system. Although the canonical signed digit representation is commonly used as it guarantees the minimal number of additions for a constant multiplication, we propose in this paper a digital filter synthesis algorithm that is based on the minimal signed digit (MSD) representation. The MSD representation is attractive because it provides a number of forms that have the minimal number of non-zero digits for a constant. This redundancy can lead to efficient filters if a proper MSD representation is selected for each constant. In experimental results, the proposed algorithm resulted in superior filters to those generated from the CSD representation.