IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Search algorithms for the multiple constant multiplications problem: Exact and approximate
Microprocessors & Microsystems
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subtraction operations. Since power dissipation is directly related to the amount of hardware, some power reduction is indirectly achieved by these algorithms. However, in many cases, glitching plays an equally important role in defining the power consumption. This is specially true for arithmetic circuits, and in particular to MCM due to high logic depth and large number of re-convergent paths. This paper introduces exact algorithms that search the optimal area of an MCM design at gate-level where each constant multiplication is implemented in its minimum depth. Experimental results show that the proposed algorithms lead to MCM designs consuming significantly less power with respect to those obtained by the MCM algorithms.