Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Shape-Adaptive DCT Algorithm - Hardware Optimized Redesign
CAIP '01 Proceedings of the 9th International Conference on Computer Analysis of Images and Patterns
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder
Integration, the VLSI Journal
High Performance Array Processor for Video Decoding
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip
Journal of VLSI Signal Processing Systems
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
A pipelined 8×8 2-D forward DCT hardware architecture for H.264/AVC high profile encoder
PSIVT'07 Proceedings of the 2nd Pacific Rim conference on Advances in image and video technology
Low power DCT using highly scalable multipliers
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
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This paper presents a cost-effective processor core design that features the simplest hardware and is suitable for discrete cosine transform/indiscrete cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two-dimensional DCT algorithm, the bit level adder-based distributed arithmetic, and common subexpression sharing to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easily scaled for higher throughput rate requirements. The DCT design has been implemented by 0.6 μm SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm 2. The proposed design can meet real-time DCT/IDCT requirements of the H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional computing power for other operations when operating at 33 MHz