Basic VLSI design (3rd ed.)
Low-power architectural design methodologies
Low-power architectural design methodologies
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Practical low power digital VLSI design
Practical low power digital VLSI design
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
Detecting Faces in Images: A Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Digital Signal Processing for Multimedia Systems
Digital Signal Processing for Multimedia Systems
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Integrated Hardware-Software Platform for Image Processing Applications
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Standard Codecs: Image Compression to Advanced Video Coding
Standard Codecs: Image Compression to Advanced Video Coding
Instruction level and operating system profiling for energy exposed software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimisation of constant matrix multiplication operation hardware using a genetic algorithm
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
Power consumption characterisation of the texas instruments TMS320VC5510 DSP
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Low-power multiplierless DCT architecture using image correlation
IEEE Transactions on Consumer Electronics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The MPEG-4 video standard verification model
IEEE Transactions on Circuits and Systems for Video Technology
Face segmentation using skin-color map in videophone applications
IEEE Transactions on Circuits and Systems for Video Technology
MPEG-4 standardized methods for the compression of arbitrarily shaped video objects
IEEE Transactions on Circuits and Systems for Video Technology
A simple processor core design for DCT/IDCT
IEEE Transactions on Circuits and Systems for Video Technology
Flexible architectures for DCT of variable-length targeting shape-adaptive transform
IEEE Transactions on Circuits and Systems for Video Technology
A VLSI architecture for video-object segmentation
IEEE Transactions on Circuits and Systems for Video Technology
An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
A new time distributed DCT architecture for MPEG-4 hardware reference model
IEEE Transactions on Circuits and Systems for Video Technology
Shape-adaptive DCT for generic coding of video
IEEE Transactions on Circuits and Systems for Video Technology
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
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The explosive growth of the mobile multimedia industry has accentuated the need for efficient VLSI implementations of the associated computationally demanding signal processing algorithms. In particular, the short battery life caused by excessive power consumption of mobile devices has become the biggest obstacle facing truly mobile multimedia. We propose novel hardware accelerator architectures for two of the most computationally demanding algorithms of the MPEG-4 video compression standard------the forward and inverse shape adaptive discrete cosine transforms (SA-DCT/IDCT). These accelerators have been designed using general low-energy design philosophies at the algorithmic/architectural abstraction levels. The themes of these philosophies are avoiding waste and trading area/performance for power and energy gains. Each core has been synthesised targeting TSMC 0.09 μm TCBN90LP technology, and the experimental results presented in this paper show that the proposed cores improve upon the prior art.