Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
A platform for mixed HW/SW algorithm specifications for the exploration of SW and HW partitioning
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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This paper illustrates the design and implementation of an integrated hardware-software platform for image processing. This platform is versatile as it is configurable at run time, has low power consumption and requires minimal processing power from the host. Thus, the illustrated solution makes complex multimedia processing tasks feasible on handheld devices with low processing power and limited battery life. The concept is illustrated by a prototype system for image compression. The hardware part is an FPGA board that can be plugged into a standard PCMCIA socket on any portable system. The FPGA is configured at run time to perform block discrete cosine transforms (DCT). The software part running on the host computer is responsible for configuring the device at run time and sending chunks of input data and getting back the computed results. The design was tested successfully and performs 8*8 block DCT in 64 clock cycles running at 60MHz. An alternative hardware-efficient design using distributed arithmetic was also considered. The complete hardware/software prototype was integrated as a part of MPEG-4 encoder software.