Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit
Journal of VLSI Signal Processing Systems
A reconfigurable multi-function computing cache architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI
Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation
An asynchronous matrix-vector multiplier for discrete cosine transform
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A Low Power 8 × 8 Direct 2-D DCT Chip Design
Journal of VLSI Signal Processing Systems
Design and implementation of JPEG encoder IP core
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
An Efficient IDCT Processor Design for HDTV Applications
Journal of VLSI Signal Processing Systems
An Efficient Architecture for the In-Place Fast Cosine Transform
Journal of VLSI Signal Processing Systems
An efficient architecture for the in place fast cosine transform
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures
Journal of VLSI Signal Processing Systems
Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Platform-Based MPEG-4 SOC Design for Video Communications
Journal of VLSI Signal Processing Systems
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip
Journal of VLSI Signal Processing Systems
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel image processing with the block data parallel architecture
IBM Journal of Research and Development
Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor
Journal of Signal Processing Systems
An efficient post-processing using DCT domain projections onto convex sets
ICIAR'06 Proceedings of the Third international conference on Image Analysis and Recognition - Volume Part I
High speed JPEG coder based on modularized and pipelined architecture with distributed control
PCM'05 Proceedings of the 6th Pacific-Rim conference on Advances in Multimedia Information Processing - Volume Part I
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
A high performance video transform engine by using space-time scheduling strategy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper discusses the design of a combined DCT/IDCT CMOS integrated circuit for real time processing of HDTV signals. The processor operates on 8×8 blocks. Inputs include the blocked pixels that are scanned one pixel at a time, and external control signals that control the forward or inverse modes of operation. Input pixels have a precision of 9-b for the DCT and 12-b for the IDCT. The layout has been generated with a 0.8 μm CMOS library using the Mentor Graphics GDT tools and measures under 10 mm2. Critical path simulation indicates a maximum input sample rate of 100 MHz