Design and implementation of JPEG encoder IP core

Authors:
Chung-Jr Lian;Liang-Gee Chen;Hao-Chieh Chang;Yung-Chi Chang
Affiliations:
DSP/IC Design Lab., Department of Electronic Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.;DSP/IC Design Lab., Department of Electronic Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.;DSP/IC Design Lab., Department of Electronic Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.;-
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

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Abstract

A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time re-configurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-um single-poly, triple-metal process. It can run up to 40 MHz at 3.3V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc.