VLSI array processors
Design and implementation of JPEG encoder IP core
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System
Journal of VLSI Signal Processing Systems
Platform-Based MPEG-4 SOC Design for Video Communications
Journal of VLSI Signal Processing Systems
A systematic approach to design low-power video codec cores
EURASIP Journal on Embedded Systems
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This paper summarizes our design experiences of various image and video codec IPs. The design issues and methodology of custom video codecs are discussed. The design methodology can be summarized as four stages, system analysis, algorithm optimization, architecture exploration, and code development. Based on these guidelines, several design cases are presented, including the proposed JPEG, MPEG-4, and H.264 architectures.