Efficient building block based RTL code generation from synchronous data flow graphs
Proceedings of the 37th Annual Design Automation Conference
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Power Evaluation of a Handheld Computer
IEEE Micro
Efficient hardware controller synthesis for synchronous dataflow graph in system level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code Generation of Data Dominated DSP Applications for FPGA Targets
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Proceedings of the 41st annual Design Automation Conference
Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards
RSP '04 Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping
JPEG, MPEG-4, and H.264 Codec IP Development
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Component-Based Methodology for Hardware Design of a Dataflow Processing Network
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
Conversion of reference C code to dataflow model: H.264 encoder case study
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Interface overheads in embedded multimedia software
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
IEEE Transactions on Signal Processing
Hardware architecture design of video compression for multimedia communication systems
IEEE Communications Magazine
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithmic and architectural co-design of a motion-estimation engine for low-power video devices
IEEE Transactions on Circuits and Systems for Video Technology
Model-based rate control implementation for low-power video communications systems
IEEE Transactions on Circuits and Systems for Video Technology
Memory centric design of an MPEG-4 video encoder
IEEE Transactions on Circuits and Systems for Video Technology
Journal of Signal Processing Systems
Combined simulation and emulation setup for complex image processing algorithms in VHDL
Proceedings of the 6th FPGAworld Conference
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The higher resolutions and new functionality of video applications increase their throughput and processing requirements. In contrast, the energy and heat limitations of mobile devices demand low-power video cores. We propose a memory and communication centric design methodology to reach an energy-efficient dedicated implementation. First, memory optimizations are combined with algorithmic tuning. Then, a partitioning exploration introduces parallelism using a cyclo-static dataflow model that also expresses implementation-specific aspects of communication channels. Towards hardware, these channels are implemented as a restricted set of communication primitives. They enable an automated RTL development strategy for rigorous functional verification. The FPGA/ASIC design of an MPEG-4 Simple Profile video codec demonstrates the methodology. The video pipeline exploits the inherent functional parallelism of the codec and contains a tailored memory hierarchy with burst accesses to external memory. 4CIF encoding at 30 fps, consumes 71 mW in a 180 nm, 1.62 V UMC technology.